1. Field of the Invention
The present invention relates generally to semiconductor devices and, more particularly, to an improved semiconductor device having no poisoned via produced therein. The invention further relates to a method of fabricating such a semiconductor device.
2. Description of the Background Art
FIGS. 12A and 12B are schematic cross-sectional views showing a representative dynamic random access memory (DRAM) device of interest in the present invention. FIG. 12A shows a part of a peripheral circuit of the DRAM, and FIG. 12B shows a part of a memory cell region. With reference to FIGS. 12A and 12B, an insulator region 22 for isolation is formed in a surface of a semiconductor substrate 21. An impurity diffusion region 23 such as a source/drain of a field effect transistor is formed at a portion surrounded by insulator region 22. Word lines 24 of polysilicon are provided on the surface of semiconductor substrate 21 with a gate insulator film 25 interposed therebetween. Word lines 24 are formed by low pressure CVD (Chemical Vapor Deposition) employing SiH.sub.4. Word lines 24 are covered with a first interlayer insulation film 26 formed thereon and a sidewall insulation film 26a formed on sidewalls thereof. These insulation films (26, 26a) are formed by low pressure CVD using SiH.sub.4 and N.sub.2 O at a high temperature of 800.degree. to 900.degree. C.
A lower capacitor electrode 27 formed of polysilicon is connected to impurity diffusion region 23. Lower capacitor electrode 27 is covered with a capacitor dielectric film 28 which is covered with an upper capacitor electrode 29.
Upper capacitor electrode 29 is covered with a second interlayer insulation film 30. When capacitor electrodes (27, 29) of polysilicon are formed by low pressure CVD, a PH.sub.3 gas may be added in order to dope phosphorus.
Bit lines 32 formed on second interlayer insulation film 30 are connected through a contact hole 31 to impurity diffusion region 23. Bit lines 32 are formed of an alloy of tungsten and silicon by low pressure CVD or sputtering. Bit lines 32 are covered with a third interlayer insulation film 33.
A first aluminum alloy interconnection 34 is formed on third interlayer insulation film 33 with a barrier metal 34a interposed therebetween. First aluminum alloy interconnection 34 is connected through a contact hole 38 to one of impurity diffusion regions 23. Barrier metal 34a is formed by sputtering TiN, TiW or the like. First aluminum alloy interconnection 34 is formed by sputtering an aluminum alloy containing silicon or copper. First aluminum alloy interconnection 34 is covered with a fourth interlayer insulation film 35.
A second aluminum alloy interconnection 36 is further formed on fourth interlayer insulation film 35 with a barrier metal 36a interposed therebetween. Second aluminum alloy interconnection 36 is connected through a contact hole 39 to first aluminum alloy interconnection 34. Second aluminum alloy interconnection 36 is covered with a passivation film 37 made of a silicon nitride. Passivation film 37 is formed by plasma employing SiH.sub.4 and NH.sub.3.
The present invention is directed to an improvement for preventing a poisoned via produced in formation of a via hole (the term with a broad concept including a contact hole and a through-hole) in an interlayer insulation film in a process of manufacturing the above-described DRAM device.
FIG. 13 is a cross-sectional view of a semiconductor device showing the state of production of a poisoned via, observed in the conventional step of forming an interlayer insulation film.
With reference to FIG. 13, a first silicon oxide film 3 is formed on a semiconductor substrate 1 to cover a first conductor pattern 2 by employing a plasma chemical vapor deposition. A solution of polysilanol having a chemical structural formula shown in FIG. 2 (which is dissolved in methanol, isopropyl alcohol or the like) is spin-coated onto first silicon oxide film 3. A resultant film is then subjected to a thermal treatment at 150.degree.-450.degree. C., to volatilize a solvent, thereby forming a coat 4. The spin-coating of the polysilanol solution onto first silicon oxide film 3 is made in order to planarize a surface of first silicon oxide film 3.
A hardening processing of coat 4 is carried out as follows. The semiconductor substrate is disposed in a vacuum chamber. An oxygen gas is applied to flow in the vacuum chamber at a flow rate of 4500 SCCM. A pressure in the vacuum chamber is set to 1.5 Torr. A high frequency wave of 13.65 MHz is applied to the electrode at output power of 800 W, thereby to generate oxygen plasma in the vacuum chamber. Semiconductor substrate 1 is exposed to this oxygen plasma for 10 minutes, so that coat 4 undergoes a plasma processing. The plasma processing advances hardening of coat 4, i.e., a three-dimensional implementation of the coat, as shown in FIG. 3. The resultant film is further subjected to a thermal treatment at a temperature of 450.degree. C. for 15 minutes in a nitrogen atmosphere for a further hardening reaction.
Referring again to FIG. 13, a second plasma oxide film 6 is formed on coat 4. Thus, an interlayer insulation film 100 including first plasma oxide film 3, coat 4 and second plasma oxide film 6 is formed. A via hole 101 for exposing a portion of the surface of first conductor pattern 2 is formed in interlayer insulation film 100. A second conductor pattern 7 connected to first conductor pattern 2 is buried in via hole 101 by sputtering.
Since the conventional interlayer insulation film is formed by the foregoing method, a crosslinking reaction of polysilanol is not sufficiently advanced, and hence a large number of free hydroxyl groups remain within the coat, with reference to FIG. 3. Thus, there is such a disadvantage that coat 4 contains a high amount of moisture. If the moisture content of coat 4 is high, moisture absorbed in coat 4 is exerted into via hole 101 upon burying of second conductor pattern 7 into via hole 101 by sputtering after formation of via hole 101 in interlayer insulation film 100. Consequently, a sputtered metal no longer adheres precisely onto wall surfaces of via hole 101, resulting in production of a poisoned via.